1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and a method of fabricating an LCD device, and more particularly to an LCD panel device and a fabricating method of fabricating an LCD panel device.
2. Description of the Related Art
In general, an LCD device controls transmission of light through liquid crystal material by application of an electric field thereto, thereby displaying an image. The LCD device drives the liquid crystal material by varying the electric field formed between a pixel electrode and a common electrode arranged in opposition to each other on upper and lower substrates.
The LCD device includes a lower array substrate (i.e., thin film transistor (TFT) array substrate) and an upper array substrate (i.e., color filter array substrate) that are coupled together. Accordingly, a spacer is disposed between the upper and lower substrates in order to maintain a uniform cell gap between the upper and lower substrates, wherein a liquid crystal material is filled within the cell gap.
The lower array substrate includes a plurality of signal wirings and TFTs, and an alignment film coated thereon to maintain alignment of the liquid crystal material. The upper array substrate includes a color filter for producing colored light, a black matrix for preventing light leakage, and an alignment film coated thereon to maintain alignment of the liquid crystal material.
Fabrication of the lower array substrate includes relatively complicated fabrication processes, such as various semiconductor processes that require a plurality of mask processes, thereby increasing manufacturing cost of the LCD panel device. Consequently, development of the lower array substrate has been directed toward reducing the total number of individual mask processes. For example, a single mask process may include many various sub-processes, such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, and inspection. Presently, a four-round mask process has been developed that excludes one mask process from the currently-used five-round mask process.
FIG. 1 is a plan view of a lower array substrate of an LCD panel device according to the related art, and FIG. 2 is a cross sectional view along II-II′ of FIG. 1 according to the related art. In FIGS. 1 and 2, a lower array substrate of an LCD panel device includes a gate line 2 and a data line 4 provided on a lower substrate 1 in such a manner as to intersect each other having a gate insulating film 12 therebetween, a TFT 30 provided at each of the intersections, a pixel electrode 22 provided at a cell area defined by the intersections, a storage capacitor 40 provided at an overlapping portion between the gate line 2 and a storage electrode 28, a gate pad 50 connected to the gate line 2, and a data pad 60 connected to the data line 4. Accordingly, the gate line 2 transmits gate signals and the data line 4 transmits data signals.
The TFT 30 allows a pixel signal transmitted along the data line 4 to be charged into the pixel electrode 22 and maintained in response to a gate signal transmitted along the gate line 2. The TFT 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22. Furthermore, the TFT 30 includes an active layer 14 overlapping the gate electrode 6 and having a gate insulating film 12 therebetween to define a channel between the source electrode 8 and the drain electrode 10. In addition, the active layer 14 overlaps with the data line 4, a lower data pad electrode 62, and a storage electrode 28. Furthermore, an ohmic contract layer is provided on the active layer 14 for making electrical contact with the data line 4, the source electrode 8, the drain electrode 10, the lower data pad electrode 62, and the storage electrode 22.
The pixel electrode 22 is connected, via a first contact hole 20 passing through a protective film 18, to the drain electrode 10 of the thin film transistor 30, and is provided at a pixel area 5. Accordingly, an electric field is created between the pixel electrode 22 to which a pixel signal is supplied via the TFT 30 and a common electrode (not shown) to which a reference voltage is supplied. Thus, liquid crystal molecules between the lower array substrate and the upper array substrate are rotated by such the electric field due to a dielectric anisotropy of the liquid crystal material. Therefore, light transmittance through the pixel area 5 is differentiated depending upon a degree of rotation of the liquid crystal molecules, thereby implementing a gray level scale.
The storage capacitor 40 includes the gate line 2, a storage electrode 28 overlapping with the gate line 2 having the gate insulating film 12, the active layer 14, and the ohmic contact layer 16 therebetween. Accordingly, the storage electrode 28 is connected, via a second contact hole 42 defined at the protective film 18, to the pixel electrode 22. Thus, the storage capacitor 40 allows a pixel signal charged to the pixel electrode 22 to be maintained until the next subsequent pixel signal is charged to the pixel electrode 22.
The gate pad 50 is connected to a gate driver (not shown) to supply gate signals to the gate line 2, and includes a lower gate pad electrode 52 extending from the gate line 2, and an upper gate pad electrode 54 connected, via a third contact hole 56 passing through the gate insulating film 12 and the protective film 18, to the lower gate pad electrode 52.
The data pad 60 is connected to a data driver (not shown) to supply data signals to the data line 4, and includes a lower data pad electrode 62 extending from the data line 4, and an upper data pad electrode 64 connected, via a fourth contact hole 66 passing through the protective film 18, to an upper data pad electrode 64 connected to the lower data pad electrode 62.
FIGS. 3A to 3D are cross sectional views of a method of fabricating the lower array substrate of FIG. 2 according to the related art. In FIG. 3A, gate metal patterns including the gate line 2, the gate electrode 6, and the lower gate pad electrode 52 are provided on the lower substrate 1 using a first mask process. For example, a gate metal layer is formed on the lower substrate 1 by a deposition technique, such as sputtering. Then, the gate metal layer is patterned by photolithography and the etching process using a first mask to form gate metal patterns including the gate line 2, the gate electrode 6, and the lower gate pad electrode 52. The gate metal layer is made from an aluminum group metal.
In FIG. 3B, the gate insulating film 12 is coated onto the lower substrate 1 provided with the gate metal patterns. Then, semiconductor patterns including the active layer 14 and the ohmic contact layer 16, and data patterns including the data line 4, the source electrode 8, the drain electrode 10, the lower data pad electrode 62, and the storage electrode 28 are formed on the gate insulating film 12 by a second mask process. For example, the gate insulating film 12, an amorphous silicon layer, an n+ amorphous silicon layer, and a data metal layer are sequentially provided on the lower substrate 1 provided with the gate metal patterns by deposition techniques, such as plasma enhanced chemical vapor deposition (PECVD) and sputtering. Accordingly, the gate insulating film 12 is formed from an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiOx), and the data metal is selected from molybdenum (Mo), titanium (Ti), tantalum (Ta), or a molybdenum alloy.
Then, a photo-resist pattern is formed on the data metal layer by photolithography using a second mask. For example, a diffractive exposure mask having a diffractive exposing part at a channel portion of a TFT is used as a second mask, thereby allowing a photo-resist pattern of the channel portion to have a lower height than other source/drain pattern portion. Subsequently, the data metal layer is patterned by a wet etching process using the photo-resist pattern to provide the data patterns including the data line 4, the source electrode 8, the drain electrode 10, which is integral to the source electrode 8, and the storage electrode 28.
Next, the n+ amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photo-resist pattern to provide the ohmic contact layer 14 and the active layer 16. The photo-resist pattern having a relatively low height is removed from the channel portion by an ashing process and the data metal layer and the ohmic contact layer 16 of the channel portion are etched by the dry etching process. Thus, the active layer 14 of the channel portion is exposed to disconnect the source electrode 8 from the drain electrode 10. Then, the photo-resist pattern left on the data pattern group is removed by a stripping process.
In FIG. 3C, the protective film 18 including the first, second, third, and fourth contact holes 20, 42, 56, and 66 are formed on the gate insulating film 12 provided with the data patterns. For example, the protective film 18 is entirely formed on the gate insulating film 12 provided with the data patterns by a deposition technique, such as the plasma enhanced chemical vapor deposition (PECVD). Then, the protective film 18 is patterned by photolithography and etching processes using a third mask to define the first, second, third, and fourth contact holes 20, 42, 56, and 66. The first contact hole 20 passes through the protective film 18 to expose the drain electrode 10, whereas the second contact hole 42 passes through the protective film 18 to expose the storage electrode 28. The third contact hole 56 passes through the protective film 18 and the gate insulating film 12 to expose the lower gate pad electrode 52, whereas the fourth contact hole 66 passes through the protective film 18 to expose the lower data pad electrode 62. Accordingly, when a metal having a large dry etching ratio, such as molybdenum (Mo), is used as the data metal, the first, second, and fourth contact holes 20, 42, and 66 pass through the drain electrode 10, the storage electrode 28, and the lower data pad electrode 62, respectively, to expose side surfaces thereof. The protective film 18 is made from an inorganic insulating material identical to the gate insulating film 12, or an organic insulating material, such as an acrylic organic compound having a small dielectric constant, benzocyclobutene (BCB), or (perfluorocyclobutane (PFCB).
In FIG. 3D, transparent conductive patterns including the pixel electrode 22, the upper gate pad electrode 54, and the upper data pad electrode 64 are provided on the protective film 18 by a fourth mask process. For example, a transparent conductive film is coated onto the protective film 18 by a deposition technique, such as sputtering. Then, the transparent conductive film is patterned by photolithography and etching processes using a fourth mask to provide the transparent conductive patterns including the pixel electrode 22, the upper gate pad electrode 54, and the upper data pad electrode 64. The pixel electrode 22 is electrically connected, via the first contact hole 20, to the drain electrode 10 while being electrically connected, via the second contact hole 42, to the storage electrode 28. The upper gate pad electrode 54 is electrically connected, via the third contact hole 56, to the lower gate pad electrode 52, and the upper data pad electrode 64 is electrically connected, via the fourth contact hole 66, to the lower data pad electrode 62. The transparent conductive film is formed from indium-tin-oxide (ITO), tin-oxide (TO), indium-tin-zinc-oxide (ITZO), or indium-zinc-oxide (IZO).
The method of fabricating the lower array substrate according to the related art adopts the four-round mask process, thereby reducing the number of fabricating processes and reducing manufacturing costs proportional to the total number of fabricating processes, as compared to the five-round mask process. However, since the four-round mask process is complicated, cost reduction is limited. Thus, further simplification of the fabricating processes are necessary to further reduce manufacturing costs.